A Design Methodology Using the Inversion Coefficient for Low-Voltage Low-Power CMOS Voltage References

The current trend towards low-voltage supply and low-power (LVLP) design is mainly caused by the growing demand for battery-operated portable equipment such as watches, smart phones and implantable devices (e.g., pacemakers and hearing aids). The operation of these circuits for long periods requires a significant amount of energy from the battery. However, battery size is often a limiting factor as its volume is limited for portability. In addition, the speed and high-integration density of transistors in single dies have increased heat dissipation to critical limits. Therefore, analog and mixed-signal circuits in the aforementioned systems must operate more and more under LVLP conditions. The voltage reference is an essential component of several analog blocks such as data converters, voltage regulators and phase-locked loops. The reference must generate a precise output voltage that is ideally independent of process, supply, load and temperature variations. Currently, voltage references must be amenable to standard digital CMOS processes and thus operate with a supply bellow 1 V, while consuming few tens of nW to a few μWs. Unfortunately, the design of such voltage references for commercial purposes becomes even more complicated due to the reduced time to market constraints. Accordingly, design methodologies have been proposed to reduce the cycle time of the analog design process, and enable the designer to explore different design options quickly while evaluating their tradeoffs [1-3]. In addition, several computational tools for automatic and optimized analog design have been developed [4-6]. An analog design methodology that provides good insight leading towards optimized design is the selection of the inversion coefficient (IC) of MOS transistors [7, 8]. The inversion coefficient is a numerical measure of the channel inversion, which depends on the applied bias voltage at the MOS terminals. In other words, the IC is a normalized number that is proportional to the quantity of free carriers in the channel region. The selection of the IC enables design within weak, moderate or strong inversion operation. Transistors operating in weak and moderate inversion are important for LVLP applications due to their low drain source saturation voltage (VDSAT) and high transconductance efficiency (gm/ID). Using simple equations motivated by the EKV MOS model [9], the method in [7, 8] guides the designer in the manual selection of bias currents and transistor sizes, resulting in an optimized design. Accordingly, this paper presents a transistorlevel design methodology for low-voltage low-power CMOS voltage references that involves the selection ABSTRACT